1. Technical Field
Several aspects of the present invention relates to a semiconductor device including an NMOS transistor, a P-tap, a PMOS transistor, and an N-tap provided in a twin-well structure.
2. Related Art
In a semiconductor device S of the related art shown in FIG. 1, a low voltage VEE (e.g., −10V), which should be lower than a ground voltage VSS, and is applied to a P-tap STp for providing the voltage of a P-substrate PS, is generated by a power supply circuit P. The power supply circuit P generates the low voltage VEE by, for example, pumping-up and dividing the power supply voltage VDD (e.g., +2.8V), and at the beginning, namely when the power supply voltage VDD is applied to the power supply circuit P to which the power supply voltage VDD has not been applied yet, the power supply circuit outputs the low voltage VEE after a brief interval from the application of the power supply voltage VDD.
JP-A-10-32259 is an example of a prior art document.
However, in the stage before the power supply circuit P outputs the low voltage VEE, a line of the low voltage VEE is in a so-called “floating” condition, and moreover, under the influences of the application of the power supply voltage VDD and a parasitic capacitance (not shown) which may exist, for example, between an N-well NW to be provided with the power supply voltage VDD and a P-substrate PS to be provided with the low voltage, the low voltage VEE may reach, for example, 0.7V (=(the ground voltage VSS)+(the forward voltage drop of a first parasitic transistor tr1)) or higher. Thus, the first parasitic transistor becomes in a conductive state, and the conductive state causes the base voltage of a second parasitic transistor tr2 to drop, as a result, the second parasitic transistor tr2 also becomes in a conductive state. When both of the first and second parasitic transistors tr1, tr2 become in the conductive state, there arises a problem that a latchup described in the related art document mentioned above, namely a short circuit between the N-tap STn and the NMOS transistor TRn illustrated with an arrow in FIG. 1 might occur.